Undergraduate Research

My undergraduate research includes Research Projects and Publications. I did my inter-semester internship at Indian Space Research Organization (ISRO) and worked on the implementation of various transducer-based switching circuits. Later, I worked on FPGA based implementation of Fast IEEE Floating-Point adders. I have also worked on FPGA based lnear and non-linear controller development.

Hereby is presented an implementation of an IEEE double precision floating-point adder (FP-adder) design mentioned in the IEEE publication “DELAY OPTIMIZED IMPLEMENTATION OF IEEE FLOATING POINT ADDITION” authored by P.M. Seidel and G. Even. The adder accepts normalized numbers, supports IEEE rounding mode, and outputs the correctly normalized rounded sum/difference in the format required by the IEEE Standard. The FP-adder design achieves a low latency by combining various optimization techniques such as: A nonstandard separation into two paths, a simple rounding algorithm, unification of rounding cases for addition and subtraction, sign-magnitude computation of a difference based on one’s complement subtraction, compound adders. A technology-independent analysis and optimization of this implementation based on the Logical Effort hardware model is done and optimal gate sizes and optimal buffer insertion has been determined. The estimated delay of this optimized design at 30.6 FO4 delays for double precision operands (15.3 FO4 delays per stage between latches). It has been concluded that this algorithm has shorter latency (-13 percent) and cycle time (-22 percent) compared to the next fastest algorithm. 

Implementation of digital controllers in embedded environment suffers from the inherent problems associated with analog-digital signals interfacing in hard real-time, therefore, the control algorithms are invariantly subjected to approximations. This paper presents a novel technique for implementation of an efficient FPGA based digital Proportional-Integral-Derivative (PID) controller for the motion control of a permanent magnet DC motor. The implementation technique circumnavigates the problem of interfacing analog and digital systems in real-time. The controller is used in a speed control loop. The hardware implementation has been done on a Xilinx Spartan 3 FPGA chip. A novel technique has been adopted for the generation of the control input as a PWM signal for controlling the motor driver circuit and decoding the optical encoder data for using it for the speed feedback in the PID control loop. The VHDL algorithm for the proposed implementation has also been presented in this paper. A comparison of the experimental results with the Matlab® based simulation shows the effectiveness of the proposed method.

Any realistic system has a certain degree of known non-linearity. Therefore, the actions of the linear controllers are often rendered insufficient and not quiet matched to the level of complexity that the system demands. The backstepping approach to address the problems of non-linearities in a system is quiet effective and it has the advantage of ease in implementation at digital environment. Even so, to encounter the uncertainties of a stabilizable system an adaptive approach has been used to enhance the control algorithm.